Category: Verilog

- Verilog

8 Bit Booth Multiplier Verilog Code

Verilog Code module BoothMulti(X, Y, Z); input signed [7:0] X, Y; output signed [31:0] Z;        reg signed [31:0] Z;        reg [1:0] temp;        integer i;        reg E1;        reg [7:0] Y1;        always @ (X, Y)        begin        Z = 31’d0;        E1 = 1’d0;       …

Read More

- Verilog

Verilog Code JK Flip Flop using Case Statement

Verilog Code :JK Flip Flop using Case Statement Verilog Code  module JKFlipFlop(    input J,    input K,     input clk,    output Q,    output Qbar        );reg Q,Qbar; always@(posedge clk)begin    case({J,K})    2’b0_0:Q<=Q;    2’b0_1:Q<=1’b0;    2’b1_0:Q<=1’b1;    2’b1_1:Q<=Qbar;endcaseendendmodule  Test Bench module JK_FlipFlop_TB;     // Inputs    reg J;    reg K;     // Outputs    wire Q;    wire Qbar;…

Read More

- Verilog

Verilog Code: Decoder (3:8) using if-else

Verilog Code: Decoder (3:8) using if-else Verilog Code module Decoderusingifelse(data,out);input [2:0]data;output [7:0]out;reg [7:0]out;always@(data)begin    if(data==7)        out=1;    else if(data==6)        out=2;    else if(data==5)        out=4;    else if(data==4)        out=8;    else if(data==3)        out=16;    else if(data==2)        out=32;    else if(data==1)        out=64;    else if(data==0)        out=128;    else    out=0;endendmodule  Test Bench module DecoderTB;…

Read More