Sequential Multiplier Verilog Code

Verilog Code

module SequentialMulti(input C,input [3:0]M,input [3:0]Q,output reg [8:0]Z );
integer i;
reg [3:0]A=0;
always@(M,Q,C)
begin
Z[8:0]={C,A,Q};
for(i=0;i<4 i="i+1)</p">begin
if(Z[0]==1)
begin
Z[8:4]=Z[8:4]+M;
Z=Z>>1;
end
else
begin
Z=Z>>1;
end
end
end


endmodule

Test Bench

module SeqTB;
// Inputs
reg C;
reg [3:0] M;
reg [3:0] Q;

// Outputs
wire [8:0] Z;

// Instantiate the Unit Under Test (UUT)
SequentialMulti uut (
.C(C),
.M(M),
.Q(Q),
.Z(Z)
);

initial begin
// Initialize Inputs
C = 0;
M = 0;
Q = 0;

// Wait 100 ns for global reset to finish
#100;
C=0;
M=4'b1111;
Q=4'b1101;
       
// Add stimulus here

end
     

endmodule

Output